When node QN is flipped, the switch states of transistors
N2 and P5 will be temporarily turned ON and OFF, respectively,
and then the voltage of node Q will be changed to 0 state.
Hence, transistors P6 and N1 will be also temporarily turned
ON and OFF, respectively. However, due to the larger size of
transistor P1, the value of node S1 will be its initial value so that
transistor P2 also remains its OFF state. Therefore, the affected
node Q will be pulled up to 1 state, and then transistor N1 will
be turned ON again, and node QN will be pulled down to 0 state.
A novel RHBD 10T cell in TSMC 65-nm CMOS process is proposed
in this brief. Compared with previous hardened 10T memory
cell, the proposed cell can recover an error in any one sensitive node.
The simulation results present that the penalty introduced for the
proposed 10T cell is the increased write/read access time that may
affect its applications with high-speed requirements. However, when
considering the constraints of the target applications, compared with
other hardened memory cells, the proposed RHBD 10T cell can be
regarded as a good choice for aerospace applications as it provides
a good balance among performance, area, power, and reliability for
memories working at radiation environment.